Join As PERC Rule Deck Development Engineer At Intel | Apply Now
Job Overview:
| Company | Intel |
|---|---|
| Job Role | PERC Rule Deck Development Engineer |
| Job ID | JR0286602 |
| Work Location | India, Bangalore |
| Work Mode | Office |
| Job Type | Full time |
| Experience | 2+ years |
| Qualification | B.Tech / M.Tech / PhD |
| Salary | Not disclosed |
| Careers Page | www.intel.com |
Skills: PERC Calibre PERC ESD Python Tcl SVRF TVF Linux
Join Intel as a PERC Rule Deck Development Engineer in Bangalore!
Intel is hiring an experienced PERC Rule Deck Development Engineer in Bangalore. This full-time role involves developing and validating electrical rule checker decks to ensure design compliance.
Who Can Apply?
- Candidates with a Bachelor's degree and 10+ years of experience, Master's degree and 8+ years of experience, or PhD degree with 2+ years of experience.
- Applicants must have a background in Electrical Engineering, Computer Engineering, Electronics, or a related semiconductor field.
- Should bring experience with PERC rule development, preferably using Calibre PERC.
- Must have knowledge of ESD, latch-up, and reliability verification.
- Comfortable working on-site in Bangalore.
About Intel:
Intel is a global technology leader focused on creating world-changing technology that enables global progress and enriches lives. The company drives innovation in computing, data centers, and semiconductor manufacturing.
What You Will Do as PERC Rule Deck Development Engineer
- Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations such as ESD paths, current density, voltage stress, and floating gates.
- Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistent results between Calibre PERC, Cadence Pegasus, and Synopsys tools.
- Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules.
- Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives.
- Automation: Develop scripts using Python, SKILL, Tcl, or Perl to automate the execution, reporting, and tracking of reliability checks across different design versions.
- Documentation: Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts.
Skills Required:
Verification Tools. Experience with PERC rule development, Calibre PERC, Cadence Pegasus, and Synopsys tools.
Scripting Languages. Familiarity with SVRF, TVF, Python, SKILL, Tcl, or Perl for automation and scripting.
Core Knowledge. Understanding of ESD, latch-up, reliability verification, and advanced technology nodes.
How to Prepare
Our tips, based only on what the listing asks for:
- Brush up on PERC rule development concepts and multi-tool integration like Calibre PERC, Cadence Pegasus, and Synopsys tools.
- Review your knowledge of ESD, latch-up, and electrical reliability verification.
- Practice scripting using Python, Tcl, SVRF, TVF, or Perl for automation tasks.
- Prepare to discuss your experience working with device physicists and analog designers.
What the Listing Does Not Mention
- No salary or compensation package details are mentioned.
- No last date to apply is specified in the listing.
How to Apply: Intel
- Click the apply link to visit the official Intel careers page.
- Review the job description and eligibility requirements carefully.
- Sign in to your Workday account or create a new profile.
- Upload your updated resume and submit your application.
Do not miss this opportunity to advance your career in semiconductor design with Intel.
Important Links:
| Events | Links |
|---|---|
| Apply Now | Click Here |
| Official Careers Page | Click Here |
Frequently Asked Questions:
What qualification is required?
Required qualification: B.Tech / M.Tech / PhD. See the eligibility section above for details.
Is this a fresher job?
No, this role requires at least 2 years of experience for PhD holders, and more for Bachelor's or Master's graduates.
Where is the job located?
The role is based in Bangalore, India.
What is the work mode?
This role requires an on-site presence.
What is the job type?
It is a full-time, experienced hire position.
Stay safe: Intel does not charge any fee to apply or to give an interview. If anyone asks you for money for a job, a referral or an offer letter, it is a scam.
Source: the official Intel careers listing for this role.
Related Jobs You May Like
- Join As PDK Engineer At Intel | Apply Now
- Join As Spice Modeling Engineer At Intel | Apply Now
- Join As Data Scientist I At Mastercard | Apply Now
- Join As Associate Analyst, Insights & Enablement At Mastercard | Apply Now
Disclaimer: This job post is for information only. All applications and questions should go to Intel through the official process.
About us:
CareerFinder.co.in: At CareerFinder.co.in, we are committed to connecting individuals with top-notch job opportunities seamlessly. Explore endless possibilities for your career growth and success with us.