Join As Physical Design Automation Engineer At Intel | Apply Now
Job Overview:
| Company | Intel |
|---|---|
| Job Role | Physical Design Automation Engineer |
| Job ID | JR0288534 |
| Work Location | India, Bangalore |
| Work Mode | Office |
| Job Type | Full time |
| Experience | Experienced |
| Qualification | M.Tech / M.S. in Microelectronics |
| Salary | Not disclosed |
| Shift | Shift 1 (India) |
| Careers Page | www.intel.com |
Skills: Cadence Innovus RTL-to-GDS Tcl Scripting Static Timing Analysis VLSI Design Floorplanning

Join Intel as a Physical Design Automation Engineer in Bangalore
Intel Foundry India is hiring an experienced Physical Design Automation Engineer to work on cutting-edge process technologies. This full-time role is based in Bangalore and requires an on-site presence.
Who Can Apply?
- Candidates holding an M.Tech or M.S. degree in Microelectronics, Electronics Engineering, or an equivalent qualification from a reputed institute.
- Professionals with relevant industry experience in physical design and APR flow development.
- Applicants with expertise in Cadence Innovus Implementation System and RTL-to-GDS flows.
About Intel:
Intel is a global leader in creating world-changing technology that enables global progress and enriches lives. The Design Technology Platform team at Intel Foundry India focuses on advanced methodology development and process technology definition.
What You Will Do as Physical Design Automation Engineer
- RTL-to-GDS Flow Development: Lead the development, deployment, and continuous improvement of RTL-to-GDS flows using Cadence Innovus as the primary PnR platform.
- Physical Design Automation: Define and drive block-level implementation, floorplanning, placement, CTS, routing automation, and timing closure methodologies.
- Scripting and Tool Benchmarking: Develop Tcl-based scripts to enhance layout productivity and benchmark Cadence Innovus against Synopsys Fusion Compiler flows.
- Customer Enablement and Collaboration: Work closely with internal and external design customers, central CAD teams, and EDA vendors to provide robust automation solutions.
Skills Required:
EDA Tools & Flows. Hands-on experience with Cadence Innovus Implementation System, Synopsys Fusion Compiler, and timing sign-off tools.
Scripting & Automation. Proficiency in Tcl-based scripting to enhance layout productivity and automation.
Domain Knowledge. Strong foundation in VLSI design, semiconductor device fundamentals, and digital electronics.
How to Prepare
Our tips, based only on what the listing asks for:
- Revise your knowledge of digital timing concepts, setup, hold, and MMMC analysis.
- Brush up on Tcl-based scripting and automation techniques for layout productivity.
- Prepare to discuss your hands-on experience with Cadence Innovus or Synopsys Fusion Compiler.
- Review semiconductor device fundamentals and physical verification sign-off flows.
What the Listing Does Not Mention
- No salary or compensation package is stated in the posting.
- No last date to apply is mentioned.
- No total vacancy count is specified.
How to Apply: Intel
- Visit the official Intel careers page using the apply link provided.
- Review the job details and requirements for Job ID JR0288534.
- Submit your application and resume online.
Build the future of technology with Intel Foundry India.
Important Links:
| Events | Links |
|---|---|
| Apply Now | Click Here |
| Official Careers Page | Click Here |
Frequently Asked Questions:
What qualification is required?
Required qualification: M.Tech / M.S. in Microelectronics. See the eligibility section above for details.
Where is the job location?
The job is located in Bangalore, India.
What is the work model?
This role requires an on-site presence.
Is any application fee charged?
No, Intel does not charge any fees during the hiring process.
Stay safe: Intel does not charge any fee to apply or to give an interview. If anyone asks you for money for a job, a referral or an offer letter, it is a scam.
Source: the official Intel careers listing for this role.
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Disclaimer: This job post is for information only. All applications and questions should go to Intel through the official process.
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