Join As PCB layout Engineer At Intel | Apply Now

Join As PCB layout Engineer At Intel | Apply Now

Join As PCB layout Engineer At Intel | Apply Now

Job Overview:

CompanyIntel
Job RolePCB layout Engineer
Job IDJR0288840
Work LocationBangalore, India
Work ModeOffice
Job TypeFull time
Experience05-08 years
QualificationBachelor of Engineering
SalaryNot disclosed
ShiftShift 1 (India)
Careers Pagewww.intel.com

Skills: Cadence Allegro PCB Design Schematics HDI Microvia Gerber AutoCAD

Join As PCB layout Engineer At Intel | Apply Now

Intel is hiring a PCB layout Engineer in Bangalore

Intel Corporation is inviting applications for a PCB Layout Engineer role based in Bangalore. This full-time position involves designing and delivering advanced circuit board layouts for cutting-edge technology.

Who Can Apply?

  • Candidates who hold a Bachelor of Engineering degree.
  • Applicants with 5 to 8 years of domain experience.
  • Individuals with hands-on experience in Cadence Allegro Library and Layout Tool (Version 23.1 and 24.1).
  • Professionals skilled in developing and validating logical symbols and physical footprints using Allegro.

About Intel:

Intel is a global leader in creating world-changing technology that enables global progress and enriches lives. The company drives innovation in computing, data storage, and semiconductor solutions.

What You Will Do as PCB layout Engineer

  • PCB Layout Design: Design and deliver PCB layouts for rigid and flexible circuit boards, covering high-density, high-speed, mixed-signal, analog, digital, and RF designs.
  • Documentation and Drawings: Prepare detailed drawings, schematics, and final design packages for PCB fabrication, including assembly documentation.
  • Design Guidelines: Define and implement design guidelines and specifications to optimize manufacturing, reliability, and cost efficiency.
  • Cross-Functional Collaboration: Collaborate with electrical design, packaging, manufacturing, thermal, and mechanical teams to improve PCB design processes.
  • Integrity and Feasibility: Interface with signal and power integrity teams and conduct feasibility studies, component placement, and trace routing.

Skills Required:

Tools and Software. Hands-on experience with Cadence Allegro Library and Layout Tool, Allegro Design Workbench, and mechanical tools like Creo, Solidworks, or AutoCAD.

Design Expertise. Knowledge of high-density high-speed trace routing, component placement, stackup, impedance details, and DFA/DFM/DFT principles.

How to Prepare

Our tips, based only on what the listing asks for:

  • Brush up your knowledge on Cadence Allegro Library and Layout Tool versions 23.1 and 24.1.
  • Revise concepts related to high-density, high-speed, analog, digital, and RF PCB designs.
  • Be prepared to discuss your experience with HDI microvia technology and CES stackup details.

What the Listing Does Not Mention

  • No salary or compensation package is stated.
  • No specific application end date or deadline is provided.
  • No application fees are required.

How to Apply: Intel

  1. Go to the official Intel jobs page using the apply link.
  2. Review the job description and requirements for job ID JR0288840.
  3. Submit your application and resume online.

Check the official link for complete details and submit your application on time.

Important Links:

EventsLinks
Apply NowClick Here
Official Careers PageClick Here
Apply only through the official link.

Frequently Asked Questions:

What qualification is required?

Required qualification: Bachelor of Engineering. See the eligibility section above for details.

What is the job location?

The job is located in Bangalore, India.

Is this a remote job?

No, this role requires an on-site presence.

What is the job ID?

The job ID is JR0288840.

Stay safe: Intel does not charge any fee to apply or to give an interview. If anyone asks you for money for a job, a referral or an offer letter, it is a scam.

Source: the official Intel careers listing for this role.

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Disclaimer: This job post is for information only. All applications and questions should go to Intel through the official process.


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